µC/GUI LCD1611 Driver
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LCD1611 Driver
Supported controllers
This driver has been tested with the following LCD controllers:
Bits per pixel
The supported color depth is 4 bpp.
Interfaces
8-bit parallel (simple bus), serial (SPI4) and I2C bus interfaces are supported.
Display data RAM organization

The picture above shows the relation between the display memory and the SEG and COM lines of the LCD.
Additional RAM requirements of the driver
This LCD driver can be used with or without a display data cache. The data cache containins a complete copy of the contents of the LCD data RAM. If a cache is not used, there are no additional RAM requirements.
It is highly recommended to use this driver with a data cache for faster LCD-access. It would slow down the performance of the driver if not using a data cache very much. The amount of memory used by the cache may be calculated as follows:
Size of RAM (in bytes) = (LCD_YSIZE + 1) / 2 * LCD_XSIZE
Additional driver functions
None.
Hardware configuration
This driver accesses the hardware with a simple bus interface as
described in the "Low-Level Configuration" chapter of the user manual. The following
table lists the macros which must be defined for hardware access:
| Macro |
Description |
| LCD_INIT_CONTROLLER |
Initialization sequence for the LCD controller. |
| LCD_READ_A0 |
Reads a byte from display controller with A-line low. |
| LCD_READ_A1 |
Reads a byte from display controller with A-line high. |
| LCD_WRITE_A0 |
Writes a byte to display controller with A-line low. |
| LCD_WRITE_A1 |
Writes a byte to display controller with A-line high. |
| LCD_WRITEM_A1 |
Writes multiple bytes to LCD controller with A-line high. |
Additional configuration switches
The following table shows optional configuration switches available for this driver:
| Macro |
Description |
| LCD_CACHE |
LCD_CACHE When set to 0, no display data cache is used, which slows down the
speed of the driver. Default is 1 (cache activated). |
Special requirements for certain LCD controllers
None.
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