µC/GUI LCD66750 Driver
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LCD66750 Driver
Supported controllers
This driver has been tested with the following LCD controllers:
It should be assumed that it will also work with any controller
of similar organization.
Bits per pixel
The supported color depth is 2 bpp.
Interfaces
The driver supports 8-bit parallel (simple bus) interfaces.
Display data RAM organization
The picture above shows the relation between the display memory and the SEG and COM lines of the LCD.
Additional RAM requirements of the driver
This LCD driver may be used with or without a display data cache, containing a com- plete copy of the contents of the LCD data RAM. If a cache is not used, there are no additional RAM requirements.
It is optional (but recommended) to use this driver with a data cache for faster LCD- access. The amount of memory used by the cache may be calculated as follows:
Size of RAM (in bytes) = (LCD_XSIZE + 7) / 8 * LCD_YSIZE * 2
Additional driver functions
None.
Hardware configuration
This driver accesses the hardware with a simple bus interface. The following table lists the macros which must be defined for hardware access:
| Macro |
Description |
| LCD_INIT_CONTROLLER |
Initialization sequence for the LCD controller. |
| LCD_READ_A0 |
Read a byte from display controller with A-line low. |
| LCD_READ_A1 |
Read a byte from display controller with A-line high. |
| LCD_WRITE_A0 |
Write a byte to display controller with A-line low. |
| LCD_WRITE_A1 |
Write a byte to display controller with A-line high. |
Additional configuration switches
The following table shows optional configuration switches available for this driver:
| Macro |
Description |
| LCD_CACHE |
When set to 0, no display data cache is used, which slows down the speed of the driver. Default is 1 (cache activated). |
Special requirements for certain LCD controllers
None.
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