µC/GUI LCDXylon Driver
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LCDXylon Driver
Supported controllers
The display driver has been written to support a FPGA-based display controller from Xylon.
Bits per pixel
The supported color depth is 8 bpp.
Interfaces
16-bit parallel (full bus) mode.
Display data RAM organization
The picture above shows the relation between the display memory and the SEG and COM lines of the LCD in terms of the color depth.
Additional RAM requirements of the driver
None.
Additional driver functions
None.
Hardware configuration
This driver requires a full bus interface for hardware access. The following table lists the macros which must be defined for hardware access:
| Macro |
Description |
| LCD_INIT_CONTROLLER |
Initialization sequence for the LCD controller. |
| LCD_READ_MEM |
Read the contents of video memory of controller. |
| LCD_READ_REG |
Read the contents of a configuration register of controller. |
| LCD_WRITE_MEM |
Write to video memory (display data RAM) of controller. |
| LCD_WRITE_REG |
Write to a configuration register of controller. |
Additional configuration switches
The following table shows optional configuration switches available for this driver:
| Macro |
Description |
| LCD_USE_BITBLT |
If set to 0, it disables the BitBLT engine. If set to 1 (the default value), the driver will use all available hardware acceleration. |
| LCD_USE_BITBLT_1BPP |
If set to 0, it disables the BitBLT engine for rendering 1bpp bitmaps. If set to 1 (the default value), the driver will use the hardware acceleration. |
| LCD_USE_BITBLT_FILL |
If set to 0, it disables the BitBLT engine for filling rectangles. If set to 1 (the default value), the driver will use the hardware acceleration. |
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