MSP432 Red vs. Black

MSP432 Red vs. Black

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This topic contains 2 replies, has 2 voices, and was last updated by  Jordan Alexander 3 years, 2 months ago.

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  • #17452

    Jordan Alexander
    Participant

    I first loaded the example of uC/OSIII onto the XMS432 which is what the first version of the MCU was from Texas Instruments. Now I have gotten the newest revision (Red) and uC/OSIII will not run on this board. I have converted the code to use the newest MSPWARE and the black version still functions while the red version will not. I’m sure it is something that needs to be changed in the BSP but I haven’t found it yet. Has anyone had this problem and come up with a solution?

    #17494

    Matt Gordon
    Keymaster

    Unfortunately, Micrium does not yet have an official example project for the newer red board that you’re using. However, we’ve worked with customers who are running µC/OS-III on this hardware. The feedback from the customers is that the correct initialization of clocks and Flash memory on the red board requires a slightly different procedure than that followed by Micrium’s examples for older versions of the board. In other words, the BSP_SysInit() routine provided in the examples must be modified for the new hardware. An updated version, which was actually modified by a customer, is provided below. Micrium’s team has not yet been able to fully test this code, but the customer is using it to successfully run µC/OS-III.

    
    void  BSP_SysInit (void)
    {
        // Set 1 flash wait state for 48 MHz
        FLCTL_BANK0_RDCTL = (FLCTL_BANK0_RDCTL & ~ FLCTL_BANK0_RDCTL_WAIT_15) | FLCTL_BANK0_RDCTL_WAIT_1;
        FLCTL_BANK1_RDCTL = (FLCTL_BANK1_RDCTL & ~ FLCTL_BANK1_RDCTL_WAIT_15) | FLCTL_BANK1_RDCTL_WAIT_1;
        
                                                            /* - Configure DCO to 48MHz. Make MCLK use the DCO.   - */
        CSKEY  = CS_ACCESS_KEY;                             /* Unlock CS module for register access.                */
        CSCTL0 = 0u;                                        /* Reset tuning parameters.                             */
        CSCTL0 = DCORSEL_5;                                 /* Set DCO to 48MHz operation.                          */
        DEF_BIT_SET(CSCTL0, DCOEN);                         /* Enable DCO (digitally controlled oscillator).        */
        
                                                            /* Select DCO as the MCLK with no divider.              */
        DEF_BIT_CLR(CSCTL1, (SELM_M | DIVM_M));
        DEF_BIT_SET(CSCTL1, SELM_3);
        CSKEY = 0u;                                         /* Lock CS module to protect it from inadvertent access.*/
    
        // Flash Bank read buffering
        FLCTL_BANK0_RDCTL = FLCTL_BANK0_RDCTL | (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
        FLCTL_BANK1_RDCTL = FLCTL_BANK1_RDCTL | (FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
        
                                                            /* Enable SysTick Module                                */
        DEF_BIT_SET(BSP_SYS_REG_SCS_STCSR,
                      SYSTICK_STCSR_CLKSOURCE | SYSTICK_STCSR_ENABLE);
    
                                                            /* Set SysTick period to 1/48000                        */
        if (((CSCTL0 & DCORSEL_M) >> 16u) == 5u) {
           SYSTICK_STRVR = 48000u;
        }
                                                   
        CPU_IntEn();                                        /* Enable Interrupts.                                   */
    }
    
    • This reply was modified 3 years, 2 months ago by  Matt Gordon.
    #17671

    Jordan Alexander
    Participant

    After a bit more snooping and with a little help with what you posted I was able to get uC-OS3 working. The BSP_SysInit was in fact off. What you posted however was still outdated because the newest MSP libraries have changed. The project began working once I used the following:

    void  BSP_SysInit (void)
    {	
    	    FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL & (~FLCTL_BANK0_RDCTL_WAIT_MASK) | FLCTL_BANK0_RDCTL_WAIT_2;
    	    FLCTL->BANK1_RDCTL  = FLCTL->BANK0_RDCTL & (~FLCTL_BANK1_RDCTL_WAIT_MASK) | FLCTL_BANK1_RDCTL_WAIT_2;
    
    	    
    	    CS->KEY = CS_ACCESS_KEY ;                        // Unlock CS module for register access
    	    CS->CTL0 = 0;                            // Reset tuning parameters
    	    CS->CTL0 = CS_CTL0_DCORSEL_5;                    // Set DCO to 48MHz
    	    
    	    CS->CTL1 = CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM_3;
    	    CS->KEY = 0;
                                                                    /* - Configure DCO to 48MHz. Make MCLK use the DCO.   - */
    
                                                                    /* Enable SysTick Module                                */
    		DEF_BIT_SET(BSP_SYS_REG_SCS_STCSR,
    					SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk);
    	
    																	/* Set SysTick period to 1/48000                        */
    		if (((CS->CTL0 & CS_CTL0_DCORSEL_MASK) >> 16u) == 5u) {
    			SysTick->LOAD = 48000u;
        }
    
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