Low-Power Applications with µC/OS-III and the Freescale Kinetis KL46

As embedded developers, we are being pulled in two opposite directions. On one hand, we have an ever-increasing demand for low-power applications. On the other hand, the demand for increasingly complex applications continues to grow. Using a real-time kernel such as µC/OS-III can help you design and write a complex application while keeping footprint and power usage down.

Let’s explore the setup of µC/OS-III on the Freescale Kinetis KL46 in term of footprint and power usage. We'll look at two important configurations for low-power applications: namely, entering wait mode during idle, and a new feature in version 3.05 called the dynamic tick.

The first feature we’ll discuss is wait mode. ARM cores can enter a low-power standby mode by executing the Wait For Interrupt (WFI) instruction. When the core enters wait mode, it operates in a low-power mode, and wakes up only at the next interrupt. By default, the µC/OS-III kernel will wait in a loop when idle, which is power inefficient. However, it is possible to enter the wait mode automatically during idle, thus reducing the power usage of applications that do not use all of the available CPU time.

The second feature, the dynamic tick, is new in version 3.05 of the µC/OS-III kernel. This new feature allows the tick task to sleep until needed, thereby reducing processor usage. Before dynamic ticking, the only way to reduce the overhead of the kernel tick was to reduce the tick frequency. This has the undesirable consequence of reducing the resolution of time-related events. With dynamic ticking, a high base tick rate can be used without the accompanying increase in CPU and power usage.

To show the gains that are possible by using these two features, we’ll use the Freescale KL46 low-power MCU. When running an RTOS, the KL46 has some interesting power operating modes. For example, the Very Low Power Runtime (VLPR) mode allows ultra-low power operation while keeping enough functionality for running an RTOS. This is the operating mode we’ll use for the test. VLPR mode is interesting because when you execute the ARM WFI instruction while in this mode, the CPU will enter Very Low Power Wait (VLPW) mode. VLPW mode enables the lowest power usage possible while still maintaining a fast wake-up time.

µC/OS-III Base Setup

When configuring µC/OS-III for a low-power processor, memory footprint should be kept to a minimum. This has the benefit of reducing RAM usage and the kernel overhead. Reduced RAM and CPU usage will in turn reduce the power usage of the kernel. For this example, we'll disable most features related to debugging, such as task profiling and statistics. Additionally, soft timers require an additional task, and should be disabled when not needed.

An average configuration like this one would have the following footprint. The values in the table below include one user application task with most of the basic functions of the kernel (such as mutexes and semaphores) enabled.

Optimization ROM RAM
Size 4.3kiB 1.5kiB
Speed 4.8kiB 1.5kiB

The table shows ROM usage when optimizing for speed and size. Assuming that enough flash memory is available, optimizing for speed can bring a measurable reduction in power usage. RAM usage can be brought down even further if some of the basic features of the kernel are not needed. For example, you can remove the tick task from an application that is fully interrupt-driven, since it does not require it, thus bringing the overall RAM usage below 1kiB.

Idle Power Usage

As mentioned above, by default the kernel will spin in a loop when idling. In a low power application, it is essential to enter wait mode when idling. This can be done by registering the idle task hook with a function similar to this one:

App_OS_IdleTaskHook (void)


When entering wait mode, interrupts should be disabled as per ARM recommendation. The core will still react to an external interrupt, and interrupts will be re-enabled after waking up. After disabling interrupts, it’s also possible to perform additional power-reduction operations if desired.

Power usage is directly proportional to CPU usage. In the figure below, you can see the current drain of the KL46 running in VLPR mode when idling, with and without the WFI call.

Current Drain on the KL46

Current Drain on the KL46

The measurements were done on the KL46 tower module running at 3V. As you can see, the benefit of entering wait mode is greater at low CPU usage. In this case, we see a 40 percent decrease in idle current drain.

Dynamic Tick

The dynamic tick feature requires a special BSP to be written. Details on how to write a dynamic tick BSP can be found in the µC/OS-III porting guide. In the case of the KL46, the low power timer (LPTIMER) can be used as the tick source, since it remains available in VLPR mode. In the following table, we compare the idle power usage of four different tick rates on the KL46, with and without dynamic ticking.

Tick Rate 1 10 100 1000
Normal 170µA 175µA 225µA 691µA
Dynamic 162µA 162µA 162µA 162µA

So based on the figures above, in order to match the idle power usage of the dynamic tick mode, you would have to reduce the tick rate to a measly 1Hz. Also worth noting is that the CPU usage of the 1000Hz tick rate is very high, at around 80%. This means a 1000Hz kernel tick rate would have been too high for the 4Mhz core clock of the KL46 in VLPR mode. However with dynamic ticking, the CPU usage is now negligible.

These power saving features are not exclusive to low-power MCUs. Mid- to high-range Cortex-M chips, as well as more powerful application processors, can make use of these features.

If you want to try µC/OS-III on the KL46 you can head to the Micrium download center right now.

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